Job Description
We’re Hiring – DFT Engineer
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We’re looking for an experienced DFT Engineer with strong hands-on expertise in Siemens Tessent, ATPG, MBIST, Scan, JTAG/IJTAG, and RTL. The ideal candidate will have a strong understanding of DFT methodologies and experience debugging and improving fault coverage.
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*Design for Test (DFT) Engineer plays a crucial role in ensuring that integrated circuits (ICs) and systems-on-chip (SoCs) can be thoroughly tested for defects, reliability, and performance.
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*Hands-on experience with the Siemens Tessent (Mentor Graphics) DFT tool suite.
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*Strong understanding of DFT fundamentals, including controllability, observability, scan insertion, and scan-based testing.
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*Expertise in ATPG (Automatic Test Pattern Generation), including pattern generation, analysis, debugging, and fault coverage improvement.
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*Experience with MBIST (Memory Built-In Self-Test), including memory test architecture, implementation, and diagnostics.
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*Good knowledge of IO Test methodologies for interface and pin-level validation.
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*Strong understanding of Clock DFT and clock verification concepts.
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*Solid foundation in Digital Design and RTL (Verilog/System Verilog).
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*Experience with industry-standard DFT/ATPG EDA tools.
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*Experience in verification of DFT features, including Boundary Scan (JTAG), IJTAG, MBIST, High-Speed Scan Testing, and other DFT methodologies.
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*Excellent analytical, debugging, and problem-solving skills.