<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p> </p>
<p><strong><span data-contrast="auto"><span data-ccp-parastyle="First Paragraph" data-ccp-parastyle-defn="{"ObjectId":"276295ed-5df2-5456-988c-5fdbab071054|1","ClassId":1073872969,"Properties":[201342446,"1",201342447,"5",201342448,"1",201342449,"1",469777841,"Aptos",469777842,"Arial",469777843,"Aptos",469777844,"Aptos",201341986,"1",469769226,"Aptos,Arial",268442635,"24",335559739,"180",335559738,"180",469775450,"First Paragraph",201340122,"2",134234082,"true",134233614,"true",469778129,"FirstParagraph",335572020,"1",469775498,"Body Text",469778324,"Body Text"]}">Role Overview</span></span></strong><span data-ccp-props="{"335559738":180,"335559739":180}"> </span></p>
<p><span data-contrast="auto"><span data-ccp-parastyle="Body Text">As a Senior Design Verification Engineer, you will help define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments.</span></span><span data-ccp-props="{"335559738":180,"335559739":180}"> </span></p>
<p><span data-contrast="auto"><span data-ccp-parastyle="Body Text">This role offers the opportunity to own meaningful verification challenges within CCE2, from planning and testbench architecture through coverage closure and silicon learning. You will contribute to Astera Labs’ hyper-growth mission by helping deliver </span><span data-ccp-parastyle="Body Text">highly reliable</span><span data-ccp-parastyle="Body Text"> PCIe and </span><span data-ccp-parastyle="Body Text">UALink</span><span data-ccp-parastyle="Body Text"> connectivity products that keep AI accelerators, memory, and compute resources </span><span data-ccp-parastyle="Body Text">operating</span><span data-ccp-parastyle="Body Text"> at scale.</span></span><span data-ccp-props="{"335559738":180,"335559739":180}"> </span></p>
<p><strong><span data-contrast="auto"><span data-ccp-parastyle="Body Text">Key Responsibilities</span></span></strong><span data-ccp-props="{"335559738":180,"335559739":180}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="1"><strong><span data-contrast="auto"><span data-ccp-parastyle="Compact" data-ccp-parastyle-defn="{"ObjectId":"eafb41c0-47a4-52dc-ac6b-3b5a7536b560|1","ClassId":1073872969,"Properties":[201342446,"1",201342447,"5",201342448,"1",201342449,"1",469777841,"Aptos",469777842,"Arial",469777843,"Aptos",469777844,"Aptos",201341986,"1",469769226,"Aptos,Arial",268442635,"24",335559739,"36",335559738,"36",469775450,"Compact",201340122,"2",134234082,"true",134233614,"true",469778129,"Compact",335572020,"1",469778324,"Body Text"]}">Verification Strategy and Planning</span></span></strong><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Develop block- and subsystem-level verification plans from specifications, architecture, and design requirements.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Define test scenarios, coverage models, checkers, assertions, and scoreboards for complex switching functionality.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Review designs and verification plans with architecture and RTL teams to </span><span data-ccp-parastyle="Compact">identify</span><span data-ccp-parastyle="Compact"> corner cases early.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><strong><span data-contrast="auto"><span data-ccp-parastyle="Compact">Environment Development and Execution</span></span></strong><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Build and enhance reusable UVM-based </span><span data-ccp-parastyle="Compact">SystemVerilog</span><span data-ccp-parastyle="Compact"> testbenches, agents, sequences, monitors, and reference models.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Create directed, constrained-random, and power-on-reset scenarios spanning PCIe Gen 6/Gen 7, </span><span data-ccp-parastyle="Compact">UALink</span><span data-ccp-parastyle="Compact">, and UCI behavior.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Debug simulation failures using waveform analysis, logs, assertions, and cross-functional collaboration.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1"><strong><span data-contrast="auto"><span data-ccp-parastyle="Compact">Coverage, Quality, and Silicon Readiness</span></span></strong><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="5" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="0" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Drive functional and code coverage analysis, </span><span data-ccp-parastyle="Compact">identify</span><span data-ccp-parastyle="Compact"> verification gaps, and close coverage to agreed milestones.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="5" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Develop regression strategies and automation to improve test quality, turnaround time, and failure triage.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="5" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="2"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Partner with design and post-silicon teams on </span><span data-ccp-parastyle="Compact">issue</span><span data-ccp-parastyle="Compact"> isolation, root-cause analysis, and silicon bring-up readiness.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<p><strong><span data-contrast="auto"><span data-ccp-parastyle="First Paragraph">Basic Qualifications</span></span></strong><span data-ccp-props="{"335559738":180,"335559739":180}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Bachelor’s degree in Electrical Engineering</span><span data-ccp-parastyle="Compact">, Computer Engineering, or </span><span data-ccp-parastyle="Compact">a related</span><span data-ccp-parastyle="Compact"> technical field.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">2–5 years of experience in design verification for complex ASICs or SoCs.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Hands-on experience with </span><span data-ccp-parastyle="Compact">SystemVerilog</span><span data-ccp-parastyle="Compact"> and UVM-based verification environments.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="6" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Experience developing verification plans, testbenches, assertions, scoreboards, and functional coverage models.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="7" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Familiarity with simulation, waveform-debug, regression, and coverage tools.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="8" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Strong debugging, communication, and collaboration skills in a fast-paced product development environment.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<p><strong><span data-contrast="auto"><span data-ccp-parastyle="First Paragraph">Preferred Qualifications</span></span></strong><span data-ccp-props="{"335559738":180,"335559739":180}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="9" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Master’s degree in Electrical Engineering</span><span data-ccp-parastyle="Compact">, Computer Engineering, or </span><span data-ccp-parastyle="Compact">a related</span><span data-ccp-parastyle="Compact"> field.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="10" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Experience verifying PCIe, </span><span data-ccp-parastyle="Compact">UALink</span><span data-ccp-parastyle="Compact">, UCI, or other high-speed connectivity and switching protocols.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="11" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Knowledge of protocol checkers, formal verification, emulation, or hardware acceleration methodologies.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="12" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Experience with Python, Perl, or </span><span data-ccp-parastyle="Compact">Tcl</span><span data-ccp-parastyle="Compact"> for </span><span data-ccp-parastyle="Compact">verification</span><span data-ccp-parastyle="Compact"> automation and regression infrastructure.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="13" data-aria-level="1"><span data-contrast="auto"><span data-ccp-parastyle="Compact">Understanding of AI or data-center system architectures, including accelerator, memory, and fabric connectivity.</span></span><span data-ccp-props="{"335559738":36,"335559739":36}"> </span></li>
</ul>
<p><span data-contrast="auto"><span data-ccp-parastyle="First Paragraph">Salary range is $148,500 to $165,000 depending on experience, level, and business </span><span data-ccp-parastyle="First Paragraph">need</span><span data-ccp-parastyle="First Paragraph">. This role may be eligible for discretionary </span><span data-ccp-parastyle="First Paragraph">bonus</span><span data-ccp-parastyle="First Paragraph">, </span><span data-ccp-parastyle="First Paragraph">incentives</span><span data-ccp-parastyle="First Paragraph"> and benefits.</span></span></p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>