<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p> </p>
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<h1 class="section-header section-header--large font-primary">Design Verification Tech Lead- SerDes/PHY IP</h1>
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<div>San Jose, California, United States</div>
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<p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p>
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<h2 class="wnfdnth _1ibi0s33y _1ibi0s34u" data-pm-slice="1 1 []">Role Overview</h2>
<p class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP — the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems.</p>
<p class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">This is a high-impact, hands-on role at the heart of Astera Labs' hyper-growth story. You'll partner directly with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks that ship into the world's most advanced AI platforms, including UALink, UCIe, PCIe Gen 6/Gen 7, and Ethernet-based connectivity products.</p>
<h2 class="wnfdnth _1ibi0s33y _1ibi0s34u">Key Responsibilities</h2>
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<p class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Verification Architecture & Strategy</strong></p>
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<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows</li>
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<p class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Execution & Coverage Closure</strong></p>
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<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Execute functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up scenarios</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Lead coverage analysis and closure, debug failures with designers, and drive regressions to clean tape-out</li>
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<p class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Physical Layer & Protocol Verification</strong></p>
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<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Verify PHY behavior against industry specifications including PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet PHY standards</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Model and validate channel behavior, link training state machines, and analog handoff scenarios</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Partner with analog/AMS designers on Real Number Modeling (RNM) and behavioral models for SerDes blocks</li>
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<p class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Cross-Functional Leadership</strong></p>
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<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Mentor junior DV engineers and set technical direction across the verification team</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Collaborate with SoC integration, firmware, post-silicon validation, and customer engineering teams</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Contribute to verification IP reuse strategy and tooling improvements across product lines</li>
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<h2 class="wnfdnth _1ibi0s33y _1ibi0s34u">Basic Qualifications</h2>
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<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Bachelor's degree in Electrical Engineering, Computer Engineering, or related field</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">5+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Expert-level proficiency in SystemVerilog and UVM</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM)</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL</li>
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<h2 class="wnfdnth _1ibi0s33y _1ibi0s34u">Preferred Qualifications</h2>
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<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">MS or PhD in Electrical Engineering or Computer Engineering</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Scripting proficiency in Python or Perl for verification automation and regression management</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Experience supporting post-silicon bring-up and correlating pre-silicon coverage with silicon results</li>
<li class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Proven ability to lead technically across a multi-disciplinary team in a fast-paced environment</li>
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<p class="wnfdntt _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Salary range is $160,000 to $200,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.</p>
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<p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p>
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<p> </p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>