Job Description
Job Description
About Celestial AI
As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system's interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI's Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.
The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.
ABOUT THE ROLE
We are seeking an experienced 3DIC Package Architect with expertise in System Technology Co-optimization (STCO). The ideal candidate will have a strong background in semiconductor packaging design to drive Celestial AI's Photonic Fabric Package solutions. This role requires cross-functional design collaboration with multiple engineering groups, such as Packaging, ASIC, AMS, Photonics, Foundry, and external partners to ensure design for manufacturing, assembly, test, reliability, and cost.
ESSENTIAL DUTIES AND RESPONSIBILITIES
- 2.5D and 3D Package Architecture Definition and Execution:
- Plan, implement, and analyze stacked die packages for 2.5D, 3D, and advanced heterogeneous integration.
- Scope STCO for advanced 3D architectures by optimizing chiplet partitioning, packaging technology, and interconnect design for bandwidth density, signal integrity, yield, and power efficiency targets.
- Scope photonic fabric design technology co-optimization by working with ASIC, AMS, Photonics, and foundry partners.
- Perform architecture pathfinding for advanced die-to-die interfaces co-designing with ASIC, AMS, and Photonic teams.
- Scope thermal and power management using leading edge 3D solutions working with thermal, mechanical, and power integrity teams.
- Lead Silicon backend, Silicon interposer, and RDL based design layout for advanced packaging architectures.
- Netlist management and 3D planning for heterogeneous chiplet assemblies using the latest EDA solutions.
- Cross-Functional Collaboration:
- Work closely with package and system designers to meet overall co-design, signal, power, and thermal integrity requirements.
- Enable testability optimized for 3D stacking by partnering with DFT and Test teams.
- Supporting activities related to production and assembly of 3D packages with substrate suppliers and OSATs.
- Work with cross-functional teams and support 3D integration and architecture efforts with IP vendors and external customers.
- Actively participate in package qualification with sensitivity to physics of failures for high thermo-mechanical reliability, driving appropriate test vehicle definition and design.
- Drive ideation and innovation of advanced package solutions and specifications to advance productization efforts by Celestial AI.
QUALIFICATIONS
- Education: BS/MS/PhD in EE/ECE/MSE/ME/ChemE or related disciplines.
- Experience:5-10 years of experience in Semiconductor Packaging Architecture definition and implementation for heterogeneous integration using EDA tools.
- Technical Expertise:
- Extensive experience working with EDA tools like Cadence Integrity System Planner for 3DIC package integration.
- Netlist planning and verification experience with multi-chiplet designs across die, package and system level hierarchies.
- Familiarity with layout tools such as Cadence Virtuoso and Advanced packaging design tools such as Cadence APD.
- Knowledge and insights to deliver high density/high performance interconnects in various 2.5D/3D packaging technologies.
- Good understanding of cross-functional packaging areas: Si floor plan, package, board layout and architecture, design rules, BOM, enabling material/process technologies, thermal, mechanical, Signal/Power Integrity, design for manufacturing, assembly, test, reliability, and cost.
- Familiarity with photonics packaging is a plus but not necessary.
- Customer and Vendor Engagement:
- Proven track record of working with customers and IP vendors for architecture definition and co-design.
- Proven track record of working with foundry, OSATs and other vendors for design technology co-optimization, manufacturing, assembly, test, reliability, and cost.
- Industry Knowledge: Experience in High Speed Signaling best practices, interface standards, Thermal management, Signal and Power integrity requirements.
- Soft Skills: Strong analytical, problem-solving, cross-functional collaboration, project management, and technical presentation skills.
PREFERRED QUALIFICATIONS
- Expertise in heterogeneous integration, fan-out packaging, chiplet architectures – co-design, layout, and netlist management using EDA tools.
- Knowledge of Thermal management, Signal and Power Integrity.
- Experience in customer substrate vendor and OSAT assembly engagement to meet manufacturing and assembly requirements.
LOCATION: Santa Clara, CA
For California Location:
As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $195,000.00 - $245,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.
We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.
Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.
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