Design Verification Engineer(12+ years of work experience required)

Job Description

Title: Design Verification Engineer

Location: San Jose, CA(Onsite)

Job Type: Full Time

Job Description:

• Design Verification expertise in System Verilog /UVM Unit/Module level Verification.
• Experience in test planning and debugging complex designs
• Full silicon design lifecycle experience
• Strong background in developing UVM Testbenches from scratch

Regards

Mamatha k,

Sr. Resource Specialist,

+1 949-676-0346

Email: mamatha@yochana.com / www.yochana.com