<h3>Job Description</h3>
Job DescriptionSenior Verification EngineerAlso open to staff, principal, or senior principal level engineers!Location: Suwanee, GA 30024 | Relocation assistance provided in form of a sign-on bonusHybrid Remote: 3 days in the office per week | Reporting To: Sr. Director, EngineeringResponsibilities:
<ul>
<li>DDR5 DIMM system-level verification and PMIC IP verification </li>
<li>Collaborating with component testing verification teams across global offices</li>
<li>Interacting with design, product, and spec engineering teams internally </li>
<li>Contributing to silicon debugging as needed </li>
<li>Developing, driving, and implementing UVM SystemVerilog TestBench infrastructure </li>
<li>Developing stimulus covering, SV assertions, and scripts as necessary</li>
<li>Providing mentorship to junior engineers on the team</li>
<li>Debugging regressions and failing simulations </li>
</ul>
Requirements:
<ul>
<li>5+ years of experience in verification engineering in the semiconductor industry </li>
<li>Understanding of CMOS circuit design and experience building UVM Testbench from scratch</li>
<li>Strong understanding of DDR5 protocol or CXL 2.0 specifications</li>
<li>Experience with digital and analog simulation tools: VCS, Xcellieum, Verdi </li>
</ul>
Compensation:
<ul>
<li>$150K - $225K + Annual Bonus + Stock Options</li>
</ul>